1. Field of the Invention
This invention relates to the field of electronic multiplying and adding within data processing systems.
2. Description of the Prior Art
It is known to provide integrated circuit central processing units with dedicated hardware for performing certain arithmetic operations. Such dedicated hardware is designed to provide higher speed evaluation of certain arithmetic operations than would be available if those arithmetic operations were performed under software control by the general purpose central processing unit core logic.
It is known to provide dedicated hardware units that multiply a M-bit number by another M-bit number to produce a 2M-bit result. In the case of a 32-bit based central processing unit, two 32-bit multiplicands produce a 64-bit result. A more refined arithmetic operation one might wish to perform is multiplying two numbers together and then adding a further number.
In the case of a 32-bit machine, multiplying two 32-bit numbers together and then adding a further 32-bit number can be relatively straightforwardly achieved. However, the result of the multiplication is a 64-bit number and it is desirable that it should be possible to add a 64-bit number to the 64-bit result of the multiplication operation. A problem that arises with this is that a 32-bit machine will have a 32-bit data path structure and expanding this to a 64-bit width to cope with the 64-bit addition will introduce undesirable complication and will require a disadvantageously large amount of circuit area.